1. Field
The invention relates to methods for producing insulator structures in a semiconductor substrate, in which insulator trenches are introduced into the semiconductor substrate from a substrate surface of the semiconductor substrate, and furthermore relates to an insulator structure.
2. Background Information
In semiconductor process technology, dimensions of semiconductor devices fabricated on or in a semiconductor substrate (wafer) are continually being reduced in order to increase a yield of semiconductor devices per wafer, and to reduce a response time or a power consumption of the semiconductor devices.
In the course of processing semiconductor devices in a wafer, a sequence of process steps for shaping insulator structures is effected in a process module. For instance, insulator structures isolate interconnects arranged in an identical metallization plane electrically from one another (intermetal dielectric, IMD) or insulate conductive sections formed below a substrate surface of the semiconductor substrate from one another (shallow trench isolation, STI). In this case, the conductive sections are doped sections of the semiconductor substrate that are formed, for example, as source/drain regions of transistors, or as structures made of conductive material that are introduced into the semiconductor substrate, such as connecting lines and electrodes of capacitor structures made of doped polysilicon.
A customary insulator material for fabricating the insulator structures is silicon oxide. In this case, the silicon oxide is preferably deposited by means of a deposition process based on a high density plasma (high density plasma, chemical vapor deposition, HDP/CVD). Silicon oxide layers of high conformity are produced by means of the HPD/CVD deposition process. Insulator structures formed from such silicon oxide layers have a high density and a high quality.
Toward smaller dimensions, insulator structures between interconnects of a metallization plane are increasingly subject to a requirement that a capacitive coupling of adjacent interconnects, which initially rises with a smaller distance, be kept small by the selection of an insulator material having low permittivity (low-k dielectric). U.S. Pat. No. 6,375,744 (Murugesh et al.), for instance, discloses methods that reduce the permittivity of the deposited insulator material by the addition of fluorine-containing additives (fluorine-based additives) during the deposition process and the partial incorporation thereof into the insulator material. In this case, it is assumed that additions of electronegative fluorine, for instance, reduce the polarizability of an Si—O—F structure produced in this way and an Si—O—F structure therefore has a lower permittivity or dielectric constant than a silicon oxide without additions. For silicon oxide layers to which fluorine is added, the terms fluorinated silicate glass, FSG) and fluorine-doped silicon oxide film are customary in this context, while in order to distinguish conceptually from this, the term undoped silicon oxide is used if the silicon oxide emerges from chemical precursor compounds (precursors) without halogen components.
Insulator structures embodied in the semiconductor substrate generally emerge from a process of filling insulator trenches introduced into the semiconductor substrate from a substrate surface. Since structures of active areas formed in the semiconductor substrate are often better scaleable with regard to planar dimensionings than with regard to a vertical dimensioning with respect to the substrate surface, there is an increase in the aspect ratio AR between a depth of the insular trenches and an opening width of the insulator trenches at the substrate surface. It is foreseeable that insulator trenches having an aspect ratio AR>5:1 will be necessary for minimum feature sizes of less than 100 nanometers.
A defect-free, complete (void-free) filling of the insulator trenches is made more difficult as the aspect ratio increases. With undoped silicon oxide, using conventional HDP/CVD deposition processes, insulator trenches can be filled essentially in a defect-free manner only up to an aspect ratio of AR<4.
U.S. Pat. No. 6,372,291 (Hua et al.), for instance, discloses that adding fluorine or a fluorine compound during the deposition process positively influences the filling operation and enables a defect-free, directional filling from the trench bottom even of insulator trenches having an aspect ratio AR>4:1 to AR<7:1. It is assumed in this case that the fluorine in the form of free radicals forms an etching component, which counteracts a growth of material in the area of the trench openings and thus an accretion of the insulator trenches in the region of the trench openings before a complete filling of a lower trench region (sputtering). Consequently, the insulator trenches are filled directionally from the trench bottom (bottom-up fill).
If an insulator trench introduced in a semiconductor substrate is filled in the manner described, then an interaction disadvantageously occurs between fluorine that is outgassing or outdiffusing from the doped silicon oxide and the material of the semiconductor substrate, typically monocrystalline silicon. On account of the interaction, a low-quality oxide arises in the insulator structure along an interface with the semiconductor substrate. The low-quality oxide has, in comparison with the insulator material, a lower etching resistance that is altered with respect to customary etching processes.
FIG. 1 diagrammatically illustrates a cross-section of two insulator trenches 21 introduced into a semiconductor substrate 1 on both sides of a web 22 formed by the semiconductor substrate 1. A residual section of a protective layer 11, which is necessary for a previous processing, is arranged on the web 22. The insulator trenches 21 are filled with an insulator filling 3, which is deposited in the course of an HDP/CVD deposition process and extends beyond a substrate surface 11. Facets 30 which are typical of the HDP deposition process form above the webs 22. The material of the insulator filling 3 is fluorine-doped silicon oxide. Fluorine outgasses or outdiffuses from the insulator filling 3. At the interface with the web 22, defect areas 6 form on account of an interaction of the fluorine with the silicon of the semiconductor substrate. The silicon oxide of the insulator filling 3 is of low quality in the defect areas 6.
Usually, after the filling of the insulator trenches, insulator material deposited above the substrate surface in the course of the HDP/CVD deposition process is planarized, for instance by means of a chemical mechanical polishing method (CMP). The low-quality oxide in the defect areas is also attacked during subsequent etchings. The insulator structure is consequently caused to recede below the substrate surface in the defect areas.
After the removal of the insulator material from the sections arranged above the substrate surface, the insulator structure formed in the insulator trench has gaps at the interfaces with the semiconductor substrate. The gaps may be filled with conductive materials in subsequent process steps, for instance during the formation of conductive structures, and consequently be the cause of short circuits.
A short circuit attributable to a defect area 6 is illustrated diagrammatically in plan view in FIG. 2. The defect area 6 extends in an insulator trench 21 along a web 22 made of crystalline silicon. An insulator material filling the insulator trenches 21 is caused to recede as far as a substrate surface. Two gate conductor structures formed in each case from a gate conductor (GC) are arranged on the substrate surface and, by way of example, form mutually insulated word lines for driving transistors 73 formed in active areas 7 (AA). For this purpose, the gate conductor was deposited in a real fashion and patterned by means of an etching step. Sections of the gate conductor bearing on the substrate surface between the gate conductor structures 72 were removed during the etching step. Residual portions of the gate conductor remain in the defect area 6 below the substrate surface and consequently short-circuit the two gate conductor structures 72.
It is furthermore known that defect areas with low-quality oxide do not arise if fluorine-doped silicon oxide is deposited on a thin silicon nitride layer (nitride liner) covering the semiconductor substrate. No perceptible interaction of fluorine with the monocrystalline silicon of the semiconductor substrate occurs in this case.
FIG. 3 diagrammatically illustrates a cross section—adapted from a scanning electron microscopy (SEM) recording—through a structure comprising webs 22 and insulator trenches 21 in a semiconductor substrate 1, said structure being covered with a nitride liner 12. The trenches have a depth of 570 nm with a width of about 135 nm. The aspect ratio AR of the insulator trenches 21 is greater than 4:1. No defect areas are discernible. The insulator trenches 21 are filled without any defects.